Boolean Logic Circuit
A Boolean logic circuit is a digital electronic circuit that performs logical operations on binary inputs (0 or 1) using combinations of fundamental logic gates — AND, OR, NOT, NAND, NOR, XOR, and XNOR — to produce a binary output defined by Boolean algebra. These circuits are the building blocks of all digital computers, forming the basis of arithmetic units, control logic, and memory elements. The behavior of any combinational logic circuit can be fully described by a Boolean expression or truth table.
Truth Tables for Fundamental Logic Gates
| Gate | Inputs (A, B) | Output | Boolean Expression | CMOS Transistors |
|---|---|---|---|---|
| AND | 00, 01, 10, 11 | 0, 0, 0, 1 | Y = A · B | 4 (series NMOS + parallel PMOS) |
| OR | 00, 01, 10, 11 | 0, 1, 1, 1 | Y = A + B | 4 (parallel NMOS + series PMOS) |
| NOT | 0, 1 | 1, 0 | Y = Ā | 2 (inverter) |
| NAND | 00, 01, 10, 11 | 1, 1, 1, 0 | Y = (A · B)' | 4 (universal gate) |
| XOR | 00, 01, 10, 11 | 0, 1, 1, 0 | Y = A ⊕ B | 8 (composed from NAND) |
| XNOR | 00, 01, 10, 11 | 1, 0, 0, 1 | Y = (A ⊕ B)' | 8 (equality gate) |
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Related Terms
Microprocessor Architecture
Microprocessor architecture describes the internal organization and design of a microprocessor, including the arrangement of its arithmetic logic unit (ALU), control unit, registers, cache, buses, and instruction set, which collectively determine how the processor fetches, decodes, and executes instructions. Architectures are broadly classified as RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer), each with distinct trade-offs in instruction complexity, pipeline depth, and energy efficiency. Modern processors incorporate multiple cores, branch prediction, out-of-order execution, and deep cache hierarchies to maximize performance.
Computer Pipeline
A computer pipeline is a hardware technique that overlaps the execution of multiple instructions by dividing instruction processing into discrete sequential stages — typically fetch, decode, execute, memory access, and write-back — so that each stage operates on a different instruction simultaneously, analogous to an assembly line. Pipelining increases instruction throughput (instructions completed per second) without reducing the time to complete a single instruction (latency), ideally executing one instruction per clock cycle at steady state. Pipeline performance is limited by hazards: structural hazards (resource conflicts), data hazards (dependency between instructions), and control hazards (branches altering instruction flow).
Memory Hierarchy (computer)
The memory hierarchy in computer systems is a structured pyramid of storage levels organized by speed, cost, and capacity, where faster and more expensive memory (registers, cache) sits close to the processor and slower, cheaper, larger storage (RAM, SSD, HDD) resides farther away. The hierarchy exploits the principle of locality — programs tend to reuse recently accessed data (temporal locality) and access nearby memory addresses (spatial locality) — to make the average memory access time approach that of the fastest level. Effective hierarchy design is critical to bridging the speed gap between the processor and main memory.
Named after George Boole (1815–1864), the English mathematician who developed Boolean algebra in his 1854 work "An Investigation of the Laws of Thought." The physical implementation as electronic circuits was established by Claude Shannon's 1937 MIT thesis linking switching circuits to Boolean algebra.